A scalable shared buffer ATM switch architecture.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/AgrawalRVB95
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1995
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A scalable shared buffer ATM switch architecture.
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asynchronous transfer mode; electronic switching systems; buffer storage; field effect transistor switches; CMOS digital integrated circuits; B-ISDN; shared memory systems; switching circuits; scalable shared buffer ATM switch architecture; asynchronous transfer mode; memory bandwidth requirement; maximum crosspoint switch size; buffer memory size; access time reduction; parallel access; multiple buffer memories; 8/spl times/8 switch; CMOS technology; B-ISDN; 1 mum; 622 Mbit/s
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A scalable shared buffer ATM switch architecture.
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