A scalable analog architecture for neural networks with on-chip learning and refreshing.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/AlhalabiB95
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1995
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A scalable analog architecture for neural networks with on-chip learning and refreshing.
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analogue processing circuits; neural chips; learning (artificial intelligence); analogue storage; scalable analog architecture; neural networks; on-chip learning; on-chip refreshing; analog storage; analog functional blocks; analog pass switches; system versatility; learning speed; local analog synaptic updating scheme; unbounded scalability
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A scalable analog architecture for neural networks with on-chip learning and refreshing.
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