2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/BhattiDD06
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/glvlsi/BhattiDD06
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Jeff_Draper
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Monty_Denneau
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Rashed_Zafar_Bhatti
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1145%2F1127908.1127956
>
foaf:
homepage
<
https://doi.org/10.1145/1127908.1127956
>
dc:
identifier
DBLP conf/glvlsi/BhattiDD06
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1145%2F1127908.1127956
(xsd:string)
dcterms:
issued
2006
(xsd:gYear)
rdfs:
label
2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Jeff_Draper
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Monty_Denneau
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Rashed_Zafar_Bhatti
>
swrc:
pages
198-203
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/2006
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/glvlsi/BhattiDD06/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/glvlsi/BhattiDD06
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2006.html#BhattiDD06
>
rdfs:
seeAlso
<
https://doi.org/10.1145/1127908.1127956
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/glvlsi
>
dc:
subject
CDR, CML driver, DLL, LVDS, PLL, SerDes, duty cycle correction (DCC), jitter and skew compensation, phase detection, standard cell based serializer and deserializer circuits for high speed signaling
(xsd:string)
dc:
title
2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document