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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/glvlsi/BourbakisM95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mohammad_Mortazavi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nikolaos_G._Bourbakis>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FGLSV.1995.516036>
foaf:homepage <https://doi.org/10.1109/GLSV.1995.516036>
dc:identifier DBLP conf/glvlsi/BourbakisM95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FGLSV.1995.516036 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label An efficient building block layout methodology for compact placement. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mohammad_Mortazavi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nikolaos_G._Bourbakis>
swrc:pages 118-123 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/glvlsi/BourbakisM95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/glvlsi/BourbakisM95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi1995.html#BourbakisM95>
rdfs:seeAlso <https://doi.org/10.1109/GLSV.1995.516036>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/glvlsi>
dc:subject circuit layout CAD; network routing; formal languages; VLSI; integrated circuit layout; integrated circuit interconnections; building block layout methodology; compact placement; synthesis placement; compaction; formal language; GEOMETRIA; geometric reshapings; VLSI regulation; functional performance; connection lines; occupied chip area; neighboring relations; dead space; open holes; channels merging process; legal overlapping; local routing; global routing (xsd:string)
dc:title An efficient building block layout methodology for compact placement. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document