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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/glvlsi/CalimeraPSBMMP07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alberto_Macii>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andrea_Calimera>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Antonio_Pullini>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ashoka_Visweswara_Sathanur>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Enrico_Macii>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Luca_Benini>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Massimo_Poncino>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1228784.1228903>
foaf:homepage <https://doi.org/10.1145/1228784.1228903>
dc:identifier DBLP conf/glvlsi/CalimeraPSBMMP07 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1228784.1228903 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
rdfs:label Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alberto_Macii>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andrea_Calimera>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Antonio_Pullini>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ashoka_Visweswara_Sathanur>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Enrico_Macii>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Luca_Benini>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Massimo_Poncino>
swrc:pages 501-504 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/2007>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/glvlsi/CalimeraPSBMMP07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/glvlsi/CalimeraPSBMMP07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2007.html#CalimeraPSBMMP07>
rdfs:seeAlso <https://doi.org/10.1145/1228784.1228903>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/glvlsi>
dc:subject insertion, layout, leakage power, sleep transistor, standard-cell (xsd:string)
dc:title Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document