Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/ChabiniCAS03
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Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs.
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CMOS, digital design, performance, power consumption, retiming, supply voltage scaling
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Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs.
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