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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/glvlsi/ChengLDNW17>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Huimei_Cheng>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jeffrey_T._Draper>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ji_Li_0006>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shahin_Nazarian>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yanzhi_Wang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F3060403.3060424>
foaf:homepage <https://doi.org/10.1145/3060403.3060424>
dc:identifier DBLP conf/glvlsi/ChengLDNW17 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F3060403.3060424 (xsd:string)
dcterms:issued 2017 (xsd:gYear)
rdfs:label Deadline-Aware Joint Optimization of Sleep Transistor and Supply Voltage for FinFET Based Embedded Systems. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Huimei_Cheng>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jeffrey_T._Draper>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ji_Li_0006>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shahin_Nazarian>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yanzhi_Wang>
swrc:pages 427-430 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/2017>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/glvlsi/ChengLDNW17/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/glvlsi/ChengLDNW17>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2017.html#ChengLDNW17>
rdfs:seeAlso <https://doi.org/10.1145/3060403.3060424>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/glvlsi>
dc:title Deadline-Aware Joint Optimization of Sleep Transistor and Supply Voltage for FinFET Based Embedded Systems. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document