Thermal-aware floorplanning exploration for 3D multi-core architectures.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/CuestaAHPAM10
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2010
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Thermal-aware floorplanning exploration for 3D multi-core architectures.
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3D, MPSoC, floorplanning, temperature
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Thermal-aware floorplanning exploration for 3D multi-core architectures.
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