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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/glvlsi/GargSGJGK06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anshul_Gupta>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kanupriya_Gulati>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mario_S%E2%88%9A%C2%B0nchez>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nikhil_Jayakumar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rajesh_Garg>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sunil_P._Khatri>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1127908.1127960>
foaf:homepage <https://doi.org/10.1145/1127908.1127960>
dc:identifier DBLP conf/glvlsi/GargSGJGK06 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1127908.1127960 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label A design flow to optimize circuit delay by using standard cells and PLAs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anshul_Gupta>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kanupriya_Gulati>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mario_S%E2%88%9A%C2%B0nchez>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nikhil_Jayakumar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rajesh_Garg>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sunil_P._Khatri>
swrc:pages 217-222 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/2006>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/glvlsi/GargSGJGK06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/glvlsi/GargSGJGK06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2006.html#GargSGJGK06>
rdfs:seeAlso <https://doi.org/10.1145/1127908.1127960>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/glvlsi>
dc:subject PLA, standard cell (xsd:string)
dc:title A design flow to optimize circuit delay by using standard cells and PLAs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document