Modeling QCA for area minimization in logic synthesis. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/John_C._Lach>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Nadine_Gergel>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Shana_Craft>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1145%2F764808.764824>
foaf:homepage	<https://doi.org/10.1145/764808.764824>
dc:identifier	DBLP conf/glvlsi/GergelCL03 (xsd:string)
dc:identifier	DOI doi.org%2F10.1145%2F764808.764824 (xsd:string)
dcterms:issued	2003 (xsd:gYear)
rdfs:label	Modeling QCA for area minimization in logic synthesis. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/John_C._Lach>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Nadine_Gergel>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Shana_Craft>
swrc:pages	60-63 (xsd:string)
dcterms:partOf	<https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/2003>
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/conf/glvlsi/GergelCL03/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/conf/glvlsi/GergelCL03>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2003.html#GergelCL03>
rdfs:seeAlso	<https://doi.org/10.1145/764808.764824>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/glvlsi>
dc:subject	CAD, QCA, interconnect, logic synthesis, nanotechnology (xsd:string)
dc:title	Modeling QCA for area minimization in logic synthesis. (xsd:string)
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rdf:type	swrc:InProceedings
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