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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/glvlsi/GoudarziI08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Maziar_Goudarzi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tohru_Ishihara>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1366110.1366201>
foaf:homepage <https://doi.org/10.1145/1366110.1366201>
dc:identifier DBLP conf/glvlsi/GoudarziI08 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1366110.1366201 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
rdfs:label Instruction cache leakage reduction by changing register operands and using asymmetric sram cells. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Maziar_Goudarzi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tohru_Ishihara>
swrc:pages 383-386 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/2008>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/glvlsi/GoudarziI08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/glvlsi/GoudarziI08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2008.html#GoudarziI08>
rdfs:seeAlso <https://doi.org/10.1145/1366110.1366201>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/glvlsi>
dc:subject asymmetric sram, instruction cache, leakage, register renaming (xsd:string)
dc:title Instruction cache leakage reduction by changing register operands and using asymmetric sram cells. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document