Design limitations in deep sub-0.1¬Ķm CMOS SRAM.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/GrubeWK02
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2002
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Design limitations in deep sub-0.1¬Ķm CMOS SRAM.
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GIDL, gate leakage, on-chip cache, tunneling currents
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Design limitations in deep sub-0.1¬Ķm CMOS SRAM.
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