Automated verification of temporal properties specified as state machines in VHDL.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/HoskoteAF95
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1995
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Automated verification of temporal properties specified as state machines in VHDL.
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hardware description languages; formal verification; high level synthesis; finite state machines; sequential circuits; microprocessor chips; formal specification; automated verification methodology; temporal properties; state machines; VHDL; synchronous sequential circuit; correctness specifications; liveness properties; Viper microprocessor; Mealy FSM; compatible states
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Automated verification of temporal properties specified as state machines in VHDL.
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