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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/glvlsi/IizukaIA05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kunihiro_Asada>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Makoto_Ikeda>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tetsuya_Iizuka>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1057661.1057681>
foaf:homepage <https://doi.org/10.1145/1057661.1057681>
dc:identifier DBLP conf/glvlsi/IizukaIA05 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1057661.1057681 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label Exact minimum-width transistor placement without dual constraint for CMOS cells. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kunihiro_Asada>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Makoto_Ikeda>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tetsuya_Iizuka>
swrc:pages 74-77 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/2005>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/glvlsi/IizukaIA05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/glvlsi/IizukaIA05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2005.html#IizukaIA05>
rdfs:seeAlso <https://doi.org/10.1145/1057661.1057681>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/glvlsi>
dc:subject boolean satisfiability, exact minimum-width transistor placement, non-dual (xsd:string)
dc:title Exact minimum-width transistor placement without dual constraint for CMOS cells. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document