Characteristics of MS-CMOS logic in sub-32nm technologies.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/IrezHZ10
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2010
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Characteristics of MS-CMOS logic in sub-32nm technologies.
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MSCMOS, domino, downsizing, gate leakage reduction, hs&ls, input vector, logic overhead, noise margin, upsizing
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Characteristics of MS-CMOS logic in sub-32nm technologies.
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