Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/ItohYK07
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2007
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Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers.
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DRAM, FD-SOI, SRAM, VT variation, bulk, deep-sub-100-nm CMOS LSIs, leakage, logic gate, minimum VDD, speed variation
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Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers.
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