Macro-models for high level area and power estimation on FPGAs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/JiangTB04
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/glvlsi/JiangTB04
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Prithviraj_Banerjee
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Tianyi_Jiang
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Xiaoyong_Tang
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1145%2F988952.988992
>
foaf:
homepage
<
https://doi.org/10.1145/988952.988992
>
dc:
identifier
DBLP conf/glvlsi/JiangTB04
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1145%2F988952.988992
(xsd:string)
dcterms:
issued
2004
(xsd:gYear)
rdfs:
label
Macro-models for high level area and power estimation on FPGAs.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Prithviraj_Banerjee
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Tianyi_Jiang
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Xiaoyong_Tang
>
swrc:
pages
162-165
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/2004
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/glvlsi/JiangTB04/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/glvlsi/JiangTB04
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2004.html#JiangTB04
>
rdfs:
seeAlso
<
https://doi.org/10.1145/988952.988992
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/glvlsi
>
dc:
subject
FPGA, RTL, area estimation, high-level synthesis, model, power estimation
(xsd:string)
dc:
title
Macro-models for high level area and power estimation on FPGAs.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document