Design and management of 3D-stacked NUCA cache for chip multiprocessors.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/JungKK11
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Design and management of 3D-stacked NUCA cache for chip multiprocessors.
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Design and management of 3D-stacked NUCA cache for chip multiprocessors.
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