Uniform area timing-driven circuit implementation. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

Property	Value
dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/conf/glvlsi/KarayiannisT95>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Dimitrios_Karayiannis>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Spyros_Tragoudas>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FGLSV.1995.516015>
foaf:homepage	<https://doi.org/10.1109/GLSV.1995.516015>
dc:identifier	DBLP conf/glvlsi/KarayiannisT95 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2FGLSV.1995.516015 (xsd:string)
dcterms:issued	1995 (xsd:gYear)
rdfs:label	Uniform area timing-driven circuit implementation. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Dimitrios_Karayiannis>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Spyros_Tragoudas>
swrc:pages	2-7 (xsd:string)
dcterms:partOf	<https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/1995>
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/conf/glvlsi/KarayiannisT95/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/conf/glvlsi/KarayiannisT95>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi1995.html#KarayiannisT95>
rdfs:seeAlso	<https://doi.org/10.1109/GLSV.1995.516015>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/glvlsi>
dc:subject	circuit CAD; logic CAD; timing; sequential circuits; combinational circuits; directed graphs; computational complexity; delays; cellular arrays; circuit module; cell library; propagation delay; input-output paths; overall area; NP-hard; directed acyclic graphs; polynomial time algorithm; heuristics; combinational circuits; sequential circuits; timing-driven circuit implementation; CAD (xsd:string)
dc:title	Uniform area timing-driven circuit implementation. (xsd:string)
dc:type	<http://purl.org/dc/dcmitype/Text>
rdf:type	swrc:InProceedings
rdf:type	foaf:Document