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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/glvlsi/KhannaGT95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Krishnaiyan_Thulasiraman>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sanjay_Khanna>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shaodi_Gao>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FGLSV.1995.516055>
foaf:homepage <https://doi.org/10.1109/GLSV.1995.516055>
dc:identifier DBLP conf/glvlsi/KhannaGT95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FGLSV.1995.516055 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Parallel hierarchical global routing for general cell layout. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Krishnaiyan_Thulasiraman>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sanjay_Khanna>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shaodi_Gao>
swrc:pages 212- (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/glvlsi/KhannaGT95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/glvlsi/KhannaGT95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi1995.html#KhannaGT95>
rdfs:seeAlso <https://doi.org/10.1109/GLSV.1995.516055>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/glvlsi>
dc:subject network routing; VLSI; circuit layout CAD; integrated circuit layout; integer programming; parallel algorithms; parallel hierarchical global routing; general cell layout; routing algorithm; hierarchical decomposition strategy; parallel processing; integer programming; network flow optimization; shared-memory machine (xsd:string)
dc:title Parallel hierarchical global routing for general cell layout. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document