Design of a 5-Gb/s PRBS generator in 0.18¬Ķm CMOS process.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/LeeW04
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2004
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Design of a 5-Gb/s PRBS generator in 0.18¬Ķm CMOS process.
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CMOS, PRBS generator, current mode logic, high-speed buffer
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Design of a 5-Gb/s PRBS generator in 0.18¬Ķm CMOS process.
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