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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/glvlsi/LinLCL14>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chang-Hao_Chiu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kuen-Wey_Lin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rung-Bin_Lin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ta-Kai_Lin>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F2591513.2591601>
foaf:homepage <https://doi.org/10.1145/2591513.2591601>
dc:identifier DBLP conf/glvlsi/LinLCL14 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F2591513.2591601 (xsd:string)
dcterms:issued 2014 (xsd:gYear)
rdfs:label Logic block and design methodology for via-configurable structured ASIC using dual supply voltages. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chang-Hao_Chiu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kuen-Wey_Lin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rung-Bin_Lin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ta-Kai_Lin>
swrc:pages 111-116 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/2014>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/glvlsi/LinLCL14/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/glvlsi/LinLCL14>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2014.html#LinLCL14>
rdfs:seeAlso <https://doi.org/10.1145/2591513.2591601>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/glvlsi>
dc:title Logic block and design methodology for via-configurable structured ASIC using dual supply voltages. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document