Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/LopezFBRL05
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2005
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Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution.
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application specific integrated circuit (ASIC), clock, load capacitance, power dissipation, routing
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Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution.
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