Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/LudoviciGBB09
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Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip.
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link design techniques, network-on-chip
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Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip.
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