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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/glvlsi/MukherjeeDS03>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Arindam_Mukherjee_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Krishna_Reddy_Dusety>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rajsaktish_Sankaranarayan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F764808.764834>
foaf:homepage <https://doi.org/10.1145/764808.764834>
dc:identifier DBLP conf/glvlsi/MukherjeeDS03 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F764808.764834 (xsd:string)
dcterms:issued 2003 (xsd:gYear)
rdfs:label A practical CAD technique for reducing power/ground noise in DSM circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Arindam_Mukherjee_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Krishna_Reddy_Dusety>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rajsaktish_Sankaranarayan>
swrc:pages 96-99 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/2003>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/glvlsi/MukherjeeDS03/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/glvlsi/MukherjeeDS03>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2003.html#MukherjeeDS03>
rdfs:seeAlso <https://doi.org/10.1145/764808.764834>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/glvlsi>
dc:subject gate sizing, linear programming, low power, power/ground noise, simultaneous switching noise, timing analysis (xsd:string)
dc:title A practical CAD technique for reducing power/ground noise in DSM circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document