Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/NaseerDBDW07
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2007
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Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology.
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critical charge, single event transient, soft error
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Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology.
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