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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/glvlsi/PsarrasLMND16>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anastasios_Psarras>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chrysostomos_Nicopoulos>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Giorgos_Dimitrakopoulos>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Junghee_Lee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Pavlos_M._Mattheakis>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F2902961.2903010>
foaf:homepage <https://doi.org/10.1145/2902961.2903010>
dc:identifier DBLP conf/glvlsi/PsarrasLMND16 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F2902961.2903010 (xsd:string)
dcterms:issued 2016 (xsd:gYear)
rdfs:label A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anastasios_Psarras>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chrysostomos_Nicopoulos>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Giorgos_Dimitrakopoulos>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Junghee_Lee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Pavlos_M._Mattheakis>
swrc:pages 335-340 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/2016>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/glvlsi/PsarrasLMND16/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/glvlsi/PsarrasLMND16>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2016.html#PsarrasLMND16>
rdfs:seeAlso <https://doi.org/10.1145/2902961.2903010>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/glvlsi>
dc:title A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document