Sensitive registers: a technique for reducing the fetch bandwidth in low-power microprocessors.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/RobinsonG07
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Sensitive registers: a technique for reducing the fetch bandwidth in low-power microprocessors.
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memory bandwidth, power efficiency, processors, registers
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Sensitive registers: a technique for reducing the fetch bandwidth in low-power microprocessors.
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