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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/glvlsi/RobinsonG07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andrew_Robinson>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jim_D._Garside>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1228784.1228820>
foaf:homepage <https://doi.org/10.1145/1228784.1228820>
dc:identifier DBLP conf/glvlsi/RobinsonG07 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1228784.1228820 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
rdfs:label Sensitive registers: a technique for reducing the fetch bandwidth in low-power microprocessors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andrew_Robinson>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jim_D._Garside>
swrc:pages 138-143 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/2007>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/glvlsi/RobinsonG07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/glvlsi/RobinsonG07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2007.html#RobinsonG07>
rdfs:seeAlso <https://doi.org/10.1145/1228784.1228820>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/glvlsi>
dc:subject memory bandwidth, power efficiency, processors, registers (xsd:string)
dc:title Sensitive registers: a technique for reducing the fetch bandwidth in low-power microprocessors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document