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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/glvlsi/SalehNNPS05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hossein_Pedram>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kamran_Saleh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mehdi_Sedighi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mehrdad_Najibi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mohsen_Naderi>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1057661.1057733>
foaf:homepage <https://doi.org/10.1145/1057661.1057733>
dc:identifier DBLP conf/glvlsi/SalehNNPS05 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1057661.1057733 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label A novel clock generation scheme for globally asynchronous locally synchronous systems: an FPGA-validated approach. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hossein_Pedram>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kamran_Saleh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mehdi_Sedighi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mehrdad_Najibi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mohsen_Naderi>
swrc:pages 296-301 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/2005>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/glvlsi/SalehNNPS05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/glvlsi/SalehNNPS05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2005.html#SalehNNPS05>
rdfs:seeAlso <https://doi.org/10.1145/1057661.1057733>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/glvlsi>
dc:subject FPGA, GALS, on-chip clock generation (xsd:string)
dc:title A novel clock generation scheme for globally asynchronous locally synchronous systems: an FPGA-validated approach. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document