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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/glvlsi/SeoCCJ04>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Abhijit_Chatterjee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chung-Seok_%28Andy%29_Seo>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nan_M._Jokerst>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sang-Yeon_Cho>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F988952.989023>
foaf:homepage <https://doi.org/10.1145/988952.989023>
dc:identifier DBLP conf/glvlsi/SeoCCJ04 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F988952.989023 (xsd:string)
dcterms:issued 2004 (xsd:gYear)
rdfs:label Design and optimization of board-level optical clock distribution network for high-performance optoelectronic system-on-a-packages. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Abhijit_Chatterjee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chung-Seok_%28Andy%29_Seo>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nan_M._Jokerst>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sang-Yeon_Cho>
swrc:pages 292-297 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/2004>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/glvlsi/SeoCCJ04/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/glvlsi/SeoCCJ04>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2004.html#SeoCCJ04>
rdfs:seeAlso <https://doi.org/10.1145/988952.989023>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/glvlsi>
dc:subject H-tree, asymmetric structure, clock distribution, clock routing, optical clock distribution, optical waveguide loss modeling, optimization, optoelectronic system-on-a-package (xsd:string)
dc:title Design and optimization of board-level optical clock distribution network for high-performance optoelectronic system-on-a-packages. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document