Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/StanisavljevicGSLG07
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Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density.
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fault-tolerant architecture, high defect density, reliability of submicron and nanoelectronic systems
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Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density.
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