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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/glvlsi/TakataM09>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Taiga_Takata>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yusuke_Matsunaga>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1531542.1531622>
foaf:homepage <https://doi.org/10.1145/1531542.1531622>
dc:identifier DBLP conf/glvlsi/TakataM09 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1531542.1531622 (xsd:string)
dcterms:issued 2009 (xsd:gYear)
rdfs:label An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Taiga_Takata>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yusuke_Matsunaga>
swrc:pages 351-356 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/2009>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/glvlsi/TakataM09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/glvlsi/TakataM09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2009.html#TakataM09>
rdfs:seeAlso <https://doi.org/10.1145/1531542.1531622>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/glvlsi>
dc:subject FPGA, logic synthesis, technology mapping (xsd:string)
dc:title An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document