Variation tolerant 9T SRAM cell design. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

Property	Value
dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/conf/glvlsi/TavvaK10>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Dhireesha_Kudithipudi>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Sreeharsha_Tavva>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1145%2F1785481.1785495>
foaf:homepage	<https://doi.org/10.1145/1785481.1785495>
dc:identifier	DBLP conf/glvlsi/TavvaK10 (xsd:string)
dc:identifier	DOI doi.org%2F10.1145%2F1785481.1785495 (xsd:string)
dcterms:issued	2010 (xsd:gYear)
rdfs:label	Variation tolerant 9T SRAM cell design. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Dhireesha_Kudithipudi>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Sreeharsha_Tavva>
swrc:pages	55-60 (xsd:string)
dcterms:partOf	<https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/2010>
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/conf/glvlsi/TavvaK10/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/conf/glvlsi/TavvaK10>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2010.html#TavvaK10>
rdfs:seeAlso	<https://doi.org/10.1145/1785481.1785495>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/glvlsi>
dc:subject	bitline leakage, embedded sram, process variations, static noise margin, static random access memory (SRAM) (xsd:string)
dc:title	Variation tolerant 9T SRAM cell design. (xsd:string)
dc:type	<http://purl.org/dc/dcmitype/Text>
rdf:type	swrc:InProceedings
rdf:type	foaf:Document