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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/glvlsi/VaranelliC95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/James_M._Varanelli>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/James_P._Cohoon>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FGLSV.1995.516023>
foaf:homepage <https://doi.org/10.1109/GLSV.1995.516023>
dc:identifier DBLP conf/glvlsi/VaranelliC95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FGLSV.1995.516023 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label A two-stage simulated annealing methodology. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/James_M._Varanelli>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/James_P._Cohoon>
swrc:pages 50-53 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/glvlsi/VaranelliC95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/glvlsi/VaranelliC95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi1995.html#VaranelliC95>
rdfs:seeAlso <https://doi.org/10.1109/GLSV.1995.516023>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/glvlsi>
dc:subject simulated annealing; circuit optimisation; VLSI; circuit CAD; integrated circuit design; two-stage simulated annealing methodology; formal method; starting temperature determination; optimization problems; adaptive schedules; stop criterion; running time; problem suite; VLSI; CAD (xsd:string)
dc:title A two-stage simulated annealing methodology. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document