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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/glvlsi/WangPC20>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vasilis_F._Pavlidis>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wei_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yuanqing_Cheng>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F3386263.3406949>
foaf:homepage <https://doi.org/10.1145/3386263.3406949>
dc:identifier DBLP conf/glvlsi/WangPC20 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F3386263.3406949 (xsd:string)
dcterms:issued 2020 (xsd:gYear)
rdfs:label Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wirelength. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vasilis_F._Pavlidis>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wei_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yuanqing_Cheng>
swrc:pages 399-404 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/2020>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/glvlsi/WangPC20/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/glvlsi/WangPC20>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2020.html#WangPC20>
rdfs:seeAlso <https://doi.org/10.1145/3386263.3406949>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/glvlsi>
dc:title Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wirelength. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document