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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/glvlsi/YoussefSNB95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Habib_Youssef>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Khaled_Nassar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Muhammad_S._T._Benten>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sadiq_M._Sait>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FGLSV.1995.516037>
foaf:homepage <https://doi.org/10.1109/GLSV.1995.516037>
dc:identifier DBLP conf/glvlsi/YoussefSNB95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FGLSV.1995.516037 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Performance driven standard-cell placement using the genetic algorithm. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Habib_Youssef>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Khaled_Nassar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Muhammad_S._T._Benten>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sadiq_M._Sait>
swrc:pages 124-127 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/glvlsi/YoussefSNB95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/glvlsi/YoussefSNB95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi1995.html#YoussefSNB95>
rdfs:seeAlso <https://doi.org/10.1109/GLSV.1995.516037>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/glvlsi>
dc:subject cellular arrays; genetic algorithms; timing; integrated circuit layout; delays; logic CAD; circuit layout CAD; standard-cell placement; genetic algorithm; area; connection length; timing performance; timing-driven placer; IC design; wire length; propagation delays; critical paths; /spl alpha/-criticality; delay performance improvement (xsd:string)
dc:title Performance driven standard-cell placement using the genetic algorithm. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document