[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/glvlsi/ZaretskyMTB04>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_Zaretsky>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gaurav_Mittal>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Prithviraj_Banerjee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xiaoyong_Tang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F988952.989048>
foaf:homepage <https://doi.org/10.1145/988952.989048>
dc:identifier DBLP conf/glvlsi/ZaretskyMTB04 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F988952.989048 (xsd:string)
dcterms:issued 2004 (xsd:gYear)
rdfs:label Evaluation of scheduling and allocation algorithms while mapping assembly code onto FPGAs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_Zaretsky>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gaurav_Mittal>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Prithviraj_Banerjee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xiaoyong_Tang>
swrc:pages 397-400 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/glvlsi/2004>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/glvlsi/ZaretskyMTB04/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/glvlsi/ZaretskyMTB04>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2004.html#ZaretskyMTB04>
rdfs:seeAlso <https://doi.org/10.1145/988952.989048>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/glvlsi>
dc:subject FPGAs, binary translation, chaining, compilers, hardware synthesis, optimizations, scheduling (xsd:string)
dc:title Evaluation of scheduling and allocation algorithms while mapping assembly code onto FPGAs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document