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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/heart/SchmitzZ18>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jesse_Schmitz>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lei_Zhang_0092>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F3241793.3241812>
foaf:homepage <https://doi.org/10.1145/3241793.3241812>
dc:identifier DBLP conf/heart/SchmitzZ18 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F3241793.3241812 (xsd:string)
dcterms:issued 2018 (xsd:gYear)
rdfs:label FPGA Hardware Implementation and Optimization for Neural Network based Chaotic System Design. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jesse_Schmitz>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lei_Zhang_0092>
swrc:pages 18:1-18:6 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/heart/2018>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/heart/SchmitzZ18/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/heart/SchmitzZ18>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/heart/heart2018.html#SchmitzZ18>
rdfs:seeAlso <https://doi.org/10.1145/3241793.3241812>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/heart>
dc:title FPGA Hardware Implementation and Optimization for Neural Network based Chaotic System Design. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document