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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/hicss/AryaSD95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Howard_Sachs>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Siamak_Arya>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sreeram_Duvvuru>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FHICSS.1995.375398>
foaf:homepage <https://doi.org/10.1109/HICSS.1995.375398>
dc:identifier DBLP conf/hicss/AryaSD95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FHICSS.1995.375398 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label An architecture for high instruction level parallelism. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Howard_Sachs>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Siamak_Arya>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sreeram_Duvvuru>
swrc:pages 153-162 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/hicss/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/hicss/AryaSD95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/hicss/AryaSD95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/hicss/hicss1995.html#AryaSD95>
rdfs:seeAlso <https://doi.org/10.1109/HICSS.1995.375398>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/hicss>
dc:subject program control structures; data flow analysis; parallel architectures; parallel programming; pipeline processing; program compilers; high instruction level parallelism; parallel architecture; data flow; control flow; multiple instructions; branches; sequential order; code execution; dataflow problems; functional units; registers; condition bits; pipelining; nonblocking cache; conditional execution; speculative execution; software pipelining; hardware support; processor architecture; compiler; Software Scheduled SuperScalar (xsd:string)
dc:title An architecture for high instruction level parallelism. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document