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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/hicss/DuvvuruA95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Siamak_Arya>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sreeram_Duvvuru>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FHICSS.1995.375396>
foaf:homepage <https://doi.org/10.1109/HICSS.1995.375396>
dc:identifier DBLP conf/hicss/DuvvuruA95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FHICSS.1995.375396 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Evaluation of a branch target address cache. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Siamak_Arya>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sreeram_Duvvuru>
swrc:pages 173-180 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/hicss/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/hicss/DuvvuruA95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/hicss/DuvvuruA95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/hicss/hicss1995.html#DuvvuruA95>
rdfs:seeAlso <https://doi.org/10.1109/HICSS.1995.375396>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/hicss>
dc:subject pipeline processing; interrupts; performance evaluation; program control structures; cache storage; program compilers; storage allocation; branch target address cache evaluation; interrupt; sequential flow; instructions; pipeline bubbles; branch penalty; cycles per instruction; multiple instruction issue processors; branch resolution scheme; target instruction fetch; unpredictable branches; fully predicated processor architecture; fetch stage; branch target caching policies; cache sizes; branch target address cache; register-relative branches (xsd:string)
dc:title Evaluation of a branch target address cache. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document