Evaluation of Parallel Logic Simulation Using DVSIM. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/conf/hicss/Meister96>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Gerd_Meister>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FHICSS.1996.495487>
foaf:homepage	<https://doi.org/10.1109/HICSS.1996.495487>
dc:identifier	DBLP conf/hicss/Meister96 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2FHICSS.1996.495487 (xsd:string)
dcterms:issued	1996 (xsd:gYear)
rdfs:label	Evaluation of Parallel Logic Simulation Using DVSIM. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Gerd_Meister>
swrc:pages	397-406 (xsd:string)
dcterms:partOf	<https://dblp.l3s.de/d2r/resource/publications/conf/hicss/1996>
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/conf/hicss/Meister96/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/conf/hicss/Meister96>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/hicss/hicss1996.html#Meister96>
rdfs:seeAlso	<https://doi.org/10.1109/HICSS.1996.495487>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/hicss>
dc:subject	Distributed Simulation, Load Balancing, Parallel Logic Simulation, Partitioning and Mapping, Speed-up, VLSI Design (xsd:string)
dc:title	Evaluation of Parallel Logic Simulation Using DVSIM. (xsd:string)
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rdf:type	swrc:InProceedings
rdf:type	foaf:Document