Pentium MPP for OLTP applications.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/hicss/NataleBCWLG95
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Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/hicss/NataleBCWLG95
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/David_Wilson
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Izidor_Gertner
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Mark_Baker
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Mark_Natale
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Roger_Collins
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Stephen_Lucci
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FHICSS.1995.375405
>
foaf:
homepage
<
https://doi.org/10.1109/HICSS.1995.375405
>
dc:
identifier
DBLP conf/hicss/NataleBCWLG95
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FHICSS.1995.375405
(xsd:string)
dcterms:
issued
1995
(xsd:gYear)
rdfs:
label
Pentium MPP for OLTP applications.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/David_Wilson
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Izidor_Gertner
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Mark_Baker
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Mark_Natale
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Roger_Collins
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Stephen_Lucci
>
swrc:
pages
95-102
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/hicss/1995
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/hicss/NataleBCWLG95/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/hicss/NataleBCWLG95
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/hicss/hicss1995.html#NataleBCWLG95
>
rdfs:
seeAlso
<
https://doi.org/10.1109/HICSS.1995.375405
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/hicss
>
dc:
subject
parallel architectures; shared memory systems; random-access storage; transaction processing; Pentium MPP; OLTP applications; multi-Pentium architecture; hierarchical memory; I/O bus subsystem; Pentium processors; RAM; hierarchical architecture; multiple boards; multiple cabinets; reflective memory; massively parallel processing
(xsd:string)
dc:
title
Pentium MPP for OLTP applications.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document