VME Bus-Based Memory Channel Architecture for High Performance Computing.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/hipc/SharmaMRA99
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/hipc/SharmaMRA99
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Anupam_Mandal
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/B._Shankar_Rao
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/G._Athithan_0001
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Manuj_Sharma
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1007%2F978-3-540-46642-0%5F7
>
foaf:
homepage
<
https://doi.org/10.1007/978-3-540-46642-0_7
>
dc:
identifier
DBLP conf/hipc/SharmaMRA99
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1007%2F978-3-540-46642-0%5F7
(xsd:string)
dcterms:
issued
1999
(xsd:gYear)
rdfs:
label
VME Bus-Based Memory Channel Architecture for High Performance Computing.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Anupam_Mandal
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/B._Shankar_Rao
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/G._Athithan_0001
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Manuj_Sharma
>
swrc:
pages
45-54
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/hipc/1999
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/hipc/SharmaMRA99/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/hipc/SharmaMRA99
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/hipc/hipc1999.html#SharmaMRA99
>
rdfs:
seeAlso
<
https://doi.org/10.1007/978-3-540-46642-0_7
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/hipc
>
dc:
title
VME Bus-Based Memory Channel Architecture for High Performance Computing.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document