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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/hipc/YanagawaHIBST03>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chitaka_Iwama>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hidehiko_Tanaka>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Luong_Dinh_Hung>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Niko_Demus_Barli>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shuichi_Sakai>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yoshimitsu_Yanagawa>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-540-24596-4%5F42>
foaf:homepage <https://doi.org/10.1007/978-3-540-24596-4_42>
dc:identifier DBLP conf/hipc/YanagawaHIBST03 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-540-24596-4%5F42 (xsd:string)
dcterms:issued 2003 (xsd:gYear)
rdfs:label Complexity Analysis of a Cache Controller for Speculative Multithreading Chip Multiprocessors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chitaka_Iwama>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hidehiko_Tanaka>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Luong_Dinh_Hung>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Niko_Demus_Barli>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shuichi_Sakai>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yoshimitsu_Yanagawa>
swrc:pages 393-404 (xsd:string)
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rdfs:seeAlso <https://doi.org/10.1007/978-3-540-24596-4_42>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/hipc>
dc:title Complexity Analysis of a Cache Controller for Speculative Multithreading Chip Multiprocessors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document