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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/hipeac/GolovanevskyDZE10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alon_Dayan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ayal_Zaks>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_Edelsohn>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Olga_Golovanevsky>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-642-11515-8%5F8>
foaf:homepage <https://doi.org/10.1007/978-3-642-11515-8_8>
dc:identifier DBLP conf/hipeac/GolovanevskyDZE10 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-642-11515-8%5F8 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
rdfs:label Trace-Based Data Layout Optimizations for Multi-core Processors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alon_Dayan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ayal_Zaks>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_Edelsohn>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Olga_Golovanevsky>
swrc:pages 81-95 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/hipeac/2010>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/hipeac/GolovanevskyDZE10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/hipeac/GolovanevskyDZE10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/hipeac/hipeac2010.html#GolovanevskyDZE10>
rdfs:seeAlso <https://doi.org/10.1007/978-3-642-11515-8_8>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/hipeac>
dc:title Trace-Based Data Layout Optimizations for Multi-core Processors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document