Multi-core data analytics SoC with a flexible 1.76 Gbit/s AES-XTS cryptographic accelerator in 65 nm CMOS.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/hipeac/GurkaynakSM0MB17
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/hipeac/GurkaynakSM0MB17
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Francesco_Conti_0001
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Frank_K._G%E2%88%9A%C4%BErkaynak
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Luca_Benini
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Michael_Muehlberghuber
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Robert_Schilling
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Stefan_Mangard
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1145%2F3031836.3031840
>
foaf:
homepage
<
https://doi.org/10.1145/3031836.3031840
>
dc:
identifier
DBLP conf/hipeac/GurkaynakSM0MB17
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1145%2F3031836.3031840
(xsd:string)
dcterms:
issued
2017
(xsd:gYear)
rdfs:
label
Multi-core data analytics SoC with a flexible 1.76 Gbit/s AES-XTS cryptographic accelerator in 65 nm CMOS.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Francesco_Conti_0001
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Frank_K._G%E2%88%9A%C4%BErkaynak
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Luca_Benini
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Michael_Muehlberghuber
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Robert_Schilling
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Stefan_Mangard
>
swrc:
pages
19-24
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/hipeac/2017cs
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/hipeac/GurkaynakSM0MB17/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/hipeac/GurkaynakSM0MB17
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/hipeac/cs2017.html#GurkaynakSM0MB17
>
rdfs:
seeAlso
<
https://doi.org/10.1145/3031836.3031840
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/hipeac
>
dc:
title
Multi-core data analytics SoC with a flexible 1.76 Gbit/s AES-XTS cryptographic accelerator in 65 nm CMOS.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document