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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/hipeac/SyrivelisRKP18>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andrea_Reale>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Christian_Pinto>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dimitris_Syrivelis>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kostas_Katrinis>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F3186608.3186611>
foaf:homepage <https://doi.org/10.1145/3186608.3186611>
dc:identifier DBLP conf/hipeac/SyrivelisRKP18 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F3186608.3186611 (xsd:string)
dcterms:issued 2018 (xsd:gYear)
rdfs:label A Software-defined SoC Memory Bus Bridge Architecture for Disaggregated Computing. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andrea_Reale>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Christian_Pinto>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dimitris_Syrivelis>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kostas_Katrinis>
swrc:pages 3:1-3:4 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/hipeac/2018aistecs>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/hipeac/SyrivelisRKP18/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/hipeac/SyrivelisRKP18>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/hipeac/aistecs2018.html#SyrivelisRKP18>
rdfs:seeAlso <https://doi.org/10.1145/3186608.3186611>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/hipeac>
dc:title A Software-defined SoC Memory Bus Bridge Architecture for Disaggregated Computing. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document