[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/his/WangZYY09>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Qiang_Ye>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shihua_Yang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xiumin_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yang_Zhang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FHIS.2009.27>
foaf:homepage <https://doi.org/10.1109/HIS.2009.27>
dc:identifier DBLP conf/his/WangZYY09 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FHIS.2009.27 (xsd:string)
dcterms:issued 2009 (xsd:gYear)
rdfs:label A New Algorithm for Designing Square Root Calculators Based on FPGA with Pipeline Technology. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Qiang_Ye>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shihua_Yang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xiumin_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yang_Zhang>
swrc:pages 99-102 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/his/2009>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/his/WangZYY09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/his/WangZYY09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/his/his2009-1.html#WangZYY09>
rdfs:seeAlso <https://doi.org/10.1109/HIS.2009.27>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/his>
dc:subject pipeline; FPGA; square root; Verilog HDL; algorithm (xsd:string)
dc:title A New Algorithm for Designing Square Root Calculators Based on FPGA with Pipeline Technology. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document