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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/hotchips/NikolicVJL15>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jason_A._T._Jones>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Peter_Labaziewicz>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rama_Venkatasubramanian>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zoran_Nikolic>
foaf:homepage <http://dx.doi.org/doi.ieeecomputersociety.org%2F10.1109%2FHOTCHIPS.2015.7477330>
foaf:homepage <https://doi.ieeecomputersociety.org/10.1109/HOTCHIPS.2015.7477330>
dc:identifier DBLP conf/hotchips/NikolicVJL15 (xsd:string)
dc:identifier DOI doi.ieeecomputersociety.org%2F10.1109%2FHOTCHIPS.2015.7477330 (xsd:string)
dcterms:issued 2015 (xsd:gYear)
rdfs:label A scalable heterogeneous multicore architecture for ADAS: Presented at HOT CHIPS: A symposium on high performance chips Flint Center, Cupertino, CA. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jason_A._T._Jones>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Peter_Labaziewicz>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rama_Venkatasubramanian>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zoran_Nikolic>
swrc:pages 1-32 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/hotchips/2015>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/hotchips/NikolicVJL15/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/hotchips/NikolicVJL15>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/hotchips/hotchips2015.html#NikolicVJL15>
rdfs:seeAlso <https://doi.ieeecomputersociety.org/10.1109/HOTCHIPS.2015.7477330>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/hotchips>
dc:title A scalable heterogeneous multicore architecture for ADAS: Presented at HOT CHIPS: A symposium on high performance chips Flint Center, Cupertino, CA. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document