High-speed, high-bandwidth DRAM memory bus with crosstalk transfer logic (XTL) interface.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/hoti/OsakaKHW01
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High-speed, high-bandwidth DRAM memory bus with crosstalk transfer logic (XTL) interface.
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High-speed, high-bandwidth DRAM memory bus with crosstalk transfer logic (XTL) interface.
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